High-Density Capacitors integrated in semiconductor substrates, especially on Si, are known in the art. They have been implemented mostly as trench (or pore) capacitors for applications as RF supply-line decoupling, phase-locked loop filtering and, even more abundantly, for trench capacitors for DRAM memories. Typical capacitance densities of capacitors obtained so far here are in the order of 25 nF/mm2, but are expected to increase to 70 nF/mm2 in the near future, which capacitors comprise a dielectric ONO layer, when reducing the ONO-based layer thickness to ˜15 nm. For DRAM applications the density is expressed in fF/μm2 and is—for logic technology reasons—comparable. These capacitance densities are for many applications not high enough. So there is a need for capacitors with higher densities.
Pillar capacitors in a semiconductor device have been developed to increase capacitor density.
US2002/068369 A1 discloses a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. It is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described. By using a very dense interconnect spacing, an inter-pore capacitor structure is obtained between the metalized pores and the pore walls utilized as insulators.
It is noted that a method is disclosed to make a 3D coil. The present invention is using semiconductor deposition to make the passives and the sidewall connection between front side and back side. In fact, the US patent is only mentioning a way to connect front side and backside, which is something different.
EP0424623 A2 discloses three-dimensional semiconductor structures in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of a material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.
It is noted that to make the horizontal layer, EP0424623 needs to make a sandwich of different layers. In order to further increase a capacity density, EP0424623 needs to add more and more layers and etch a stack that is thicker and thicker. In the present invention, in order to further increase the density, one can only etch deeper and deeper, without adding a new sandwich of a different layer.
US2005135043 A2 discloses a base structure which is formed from a green material having first and second opposing sides and having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. First and second capacitor structures are formed on the sintered ceramic base structure, each on a respective side of the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill via openings in brittle substrates such as silicon substrates. Capacitor structures on opposing sides provide more capacitance without manufacturing complexities associated with the manufacture of one capacitor structure having a large number of power and ground planes.
U.S. Pat. No. 6,620,672 B1 discloses a method of fabricating a memory cell in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulating material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.
Further capacitor structures may be found in U.S. Pat. No. 5,204,280A1 (IBM, 1993), U.S. Pat. No. 5,240,558A (Motorola, 1993), U.S. Pat. No. 5,245,505A (Sumitomo, 1993), U.S. Pat. No. 5,336,630A (Goldstar, 1994), U.S. Pat. No. 5,466,626A (IBM, 1995), and U.S. Pat. No. 5,474,950A (Hyundai, 1995).
There are different parameters to play with to increase the 3D capacitance density. Making narrower or deeper pillar structures is an option, but the increase in aspect ratio makes the structures more mechanically fragile and not attractive in terms of cost. The use of other dielectric material, like high k, is an alternative solution, but again make this option expensive due to the process technology used therein. Other structures, like multiple capacitance, can only achieve high capacitance density at the expense of increasing the number of process steps.
Thus, there still is a need to provide capacitors with higher density, which do not have one or more of the above disadvantages.